1. Field of the Invention
The present invention relates to a two-wire type data communication method and system between a data storage device and a controller in a contact type data storage system, a controller and a data storage device.
2. Description of the Related Art
A contact type data storage system is used in a parts control of OA devices or a schedule control in a factory or the like. A two-wire type data communication system has been employed in a communication between a data storage device and a controller forming the contact type data storage system to make the system compact (for instance, see JP-A-2003-69653).
FIG. 13 is a voltage wave form diagram for explaining a usual two-wire type data communication method. FIG. 14 is a block diagram showing a structural example of a contact type data storage system using the usual two-wire type data communication method. In FIG. 14, the contact type data storage system comprises a controller 1201 and a data storage device 1202.
The controller 1201 includes a clock generating circuit 1205 for forming a clock pulse and a pulse of an opposite phase thereto, a voltage level generating circuit 1203 for generating the amplitude level of the clock pulse, a first transmitting circuit 1204 for changing the amplitude of the clock pulse in accordance with a transmit signal and a first signal detecting circuit 1206 for detecting an amplitude difference appearing in the clock pulse and the pulse of the opposite phase thereto.
Further, the data storage device 1202 includes a rectifying circuit 1208 for full-wave rectifying voltage from the clock pulse and the pulse of the opposite phase thereto, a data demodulating circuit 1209 for detecting the amplitude difference of the clock pulses to reproduce the transmit signal, a second transmitting circuit 1210 for changing a load impedance between two-wire type communication terminals in accordance with the transmit signal to change a voltage amplitude and a clock detecting circuit 1211 for reproducing the clock pulse.
The voltage level generating circuit 1203 includes a resistance R1 connected to a source voltage +V and a resistance R2 connected in series thereto to output the voltage Vout of a node of the resistance R1 and the resistance R2. The transmitting circuit 1204 is composed of a MOS transistor having a source and a drain respectively connected to the resistance R2 and a reference potential GND of the voltage level generating circuit 1203 and a gate to which the transmit signal is inputted to determine the output level Vout of the voltage level generating circuit 1203.
The clock generating circuit 1205 includes two stages of inverters to output clock pulses of the same phase and the opposite phase relative to a clock signal input. The electric power supply terminals of the inverters are respectively connected to the output Vout of the voltage level generating circuit 1203. The amplitudes of the clock pulses of the same phase and the opposite phase are changed in accordance with the output Vout to superimpose the transmit signal on the clock pulses and transmit the superimposed transmit signal to the data storage device 1202.
In the data storage device 1202 for receiving the clock pulse and the pulse of the opposite phase thereto, the data demodulating circuit 1209 extracts a signal component superimposed on the voltage rectified by the rectifying circuit 1208. The clock detecting circuit 1211 is composed of an inverter to reproduce the clock pulse without depending on the superimposed signal component and use the clock pulse as the clock of the data storage device 1202.
The second transmitting circuit 1210 includes a resistance and a switch connected in series between the two-wire type communication terminals of the data storage device 1202 and changes a load impedance between the terminals in accordance with the transmit signal. Thus, the second transmitting circuit changes the amplitude of the clock pulse received from the controller 1201. The signal detecting circuit 1206 is connected to either of the two-wire type communication terminals in the controller 1201 to detect the change of the amplitude of the clock pulse in these terminals as a receive signal.
FIG. 15 is a circuit diagram showing the data demodulating circuit 1209 and an operation thereof is explained by using the voltage wave form diagram of FIG. 13. Firstly, to a low-pass filter 1301, a voltage wave form on which the signal as shown in FIG. 13(e) as an output of the rectifying circuit of the data storage device is superimposed is inputted to remove noise generated due to skew or the like. Then, in a high-pass filter 1302, the leading and trailing edges of the signal are detected and the dc components of the signal are removed as shown in FIG. 13(f).
In a comparator 1303 with a hysteresis, when the output of the high-pass filter 1302 exceeds a high hystresis level, as shown in FIG. 13(g), an internal source voltage level, that is, a logic “H” is outputted. Further, when the output of the high-pass filter is lower than a low hysteresis level, an internal reference voltage level, that is, a logic “L” is outputted. Finally, in a D flip flop 1304, the output of the comparator 1303 is detected at the trailing edge of the output of the clock detecting circuit and outputted as demodulated data.
As described above, in the usual data communication method, a transmit signal component is superimposed on a transmit clock as the change of an amplitude to perform a data communication. In such a way, the signal is mutually transmitted and received and electric power and clocks are simultaneously supplied to the data storage device from the controller.
However, in the above-described usual method, when there is a timing skew between the clock pulse and the clock pulse of the opposite phase thereto as shown in FIG. 13, noise is generated in the rectified internal source voltage. At this time, when the operation of an internal circuit of an incorporated memory is superimposed on the noise, the drop of a power source noise is increased. Consequently, as shown in FIGS. 13(e) to 13(h), an erroneous data demodulation is undesirably performed in the data demodulating circuit.
When the timing skew between the clock pulse and the clock pulse of the opposite phase thereto becomes larger, this phenomenon more frequently arises. Accordingly, in the controller and the transmitting path of the two-wire type communication, a relatively strict timing adjustment is required.
Further, since a structure is designed to superimpose data on the clock pulse by modulating the amplitude and transmit the superimposed data from the controller, a ternary output voltage level is necessary. Thus, the circuit structure of the controller is complicated and the output voltage level needs to be adjusted as well as unevenness in an equivalent resistance of an internal circuit of the data storage device. Accordingly, a burden in designing a system is relatively increased.